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/ AmigActive 10 / AACD 10.iso / AACD / Games / MAME / src / cpu / mips / mipsdasm.c < prev   
C/C++ Source or Header  |  2000-04-27  |  21KB  |  608 lines
  1. /*
  2.  * MIPS disassembler for the MAME project written by smf
  3.  *
  4.  */
  5.  
  6. #include <string.h>
  7. #include <stdio.h>
  8. #include <stdlib.h>
  9. #include "mips.h"
  10.  
  11. #ifdef STANDALONE
  12. #define cpu_readop32( p ) ( ( filebuf[ p + order[ 0 ] - offset ] << 24 ) | ( filebuf[ p + order[ 1 ] - offset ] << 16 ) | ( filebuf[ p + order[ 2 ] - offset ] << 8 ) | ( filebuf[ p + order[ 3 ] - offset ] ) )
  13. #else
  14. #include "memory.h"
  15. #endif
  16.  
  17. static char *make_signed_hex_str_16( UINT32 value )
  18. {
  19.     static char s_hex[ 20 ];
  20.  
  21.     value &= 0xffff;
  22.     if( value & 0x8000 )
  23.     {
  24.         sprintf( s_hex, "-$%x", ( 0 - value ) & 0x7fff );
  25.     }
  26.     else
  27.     {
  28.         sprintf( s_hex, "$%x", value & 0x7fff );
  29.     }
  30.     return s_hex;
  31. }
  32.  
  33. static char *s_cpugenreg[] =
  34. {
  35.     "zero","at","v0","v1","a0","a1","a2","a3",
  36.     "t0","t1","t2","t3","t4","t5","t6","t7",
  37.     "s0","s1","s2","s3","s4","s5","s6","s7",
  38.     "t8","t9","k0","k1","gp","sp","fp","ra"
  39. };
  40.  
  41. static char *s_cp0genreg[] =
  42. {
  43.     "Index","Random","EntryLo","cp0r3","Context","cp0r5","cp0r6","cp0r7",
  44.     "BadVAddr","cp0r9","EntryHi","cp0r11","SR","Cause","EPC","PRId",
  45.     "cp0r16","cp0r17","cp0r18","cp0r19","cp0r20","cp0r21","cp0r22","cp0r23",
  46.     "cp0r24","cp0r25","cp0r26","cp0r27","cp0r28","cp0r29","cp0r30","cp0r31"
  47. };
  48.  
  49. static char *s_cp1genreg[] =
  50. {
  51.     "cp1r0","cp1r1","cp1r2","cp1r3","cp1r4","cp1r5","cp1r6","cp1r7",
  52.     "cp1r8","cp1r9","cp1r10","cp1r11","cp1r12","cp1r13","cp1r14","cp1r15",
  53.     "cp1r16","cp1r17","cp1r18","cp1r19","cp1r20","cp1r21","cp1r22","cp1r22",
  54.     "cp1r23","cp1r24","cp1r25","cp1r26","cp1r27","cp1r28","cp1r29","cp1r30"
  55. };
  56.  
  57. static char *s_cp1ctlreg[] =
  58. {
  59.     "cp1cr0","cp1cr1","cp1cr2","cp1cr3","cp1cr4","cp1cr5","cp1cr6","cp1cr7",
  60.     "cp1cr8","cp1cr9","cp1cr10","cp1cr11","cp1cr12","cp1cr13","cp1cr14","cp1cr15",
  61.     "cp1cr16","cp1cr17","cp1cr18","cp1cr19","cp1cr20","cp1cr21","cp1cr22","cp1cr23",
  62.     "cp1cr24","cp1cr25","cp1cr26","cp1cr27","cp1cr28","cp1cr29","cp1cr30","cp1cr31"
  63. };
  64.  
  65. static char *s_cp2genreg[] =
  66. {
  67.     "vxy0","vz0","vxy1","vz1","vxy2","vz2","rgb","otz",
  68.     "ir0","ir1","ir2","ir3","sxy0","sxy1","sxy2","sxyp",
  69.     "sz0","sz1","sz2","sz3","rgb0","rgb1","rgb2","cp2cr23",
  70.     "mac0","mac1","mac2","mac3","irgb","orgb","lzcs","lzcr"
  71. };
  72.  
  73. static char *s_cp2ctlreg[] =
  74. {
  75.     "r11r12","r13r21","r22r23","r31r32","r33","trx","try","trz",
  76.     "l11l12","l13l21","l22l23","l31l32","l33","rbk","gbk","bbk",
  77.     "lr1lr2","lr3lg1","lg2lg3","lb1lb2","lb3","rfc","gfc","bfc",
  78.     "ofx","ofy","h","dqa","dqb","zsf3","zsf4","flag"
  79. };
  80.  
  81. static char *s_gtesf[] =
  82. {
  83.     "  ","12"
  84. };
  85.  
  86. static char *s_gtemx[] =
  87. {
  88.     "multrm","multlm","multcm","nomult"
  89. };
  90.  
  91. static char *s_gtev[] =
  92. {
  93.     "v0","v1","v2","ir"
  94. };
  95.  
  96. static char *s_gtecv[] =
  97. {
  98.     "addtr","addbk","addfc","noadd"
  99. };
  100.  
  101. static char *s_gtelm[] =
  102. {
  103.     "nolimit","limit"
  104. };
  105.  
  106. unsigned DasmMIPS( char *buffer, UINT32 oldpc )
  107. {
  108.     UINT32 pc, op;
  109.  
  110.     pc = oldpc;
  111.     op = cpu_readop32( pc );
  112.     pc += 4;
  113.  
  114.     sprintf( buffer, "dw      $%08x", op );
  115.  
  116.     switch( INS_OP( op ) )
  117.     {
  118.     case OP_SPECIAL:
  119.         switch( INS_FUNCT( op ) )
  120.         {
  121.         case FUNCT_SLL:
  122.             if( op == 0 )
  123.             {
  124.                 /* the standard nop is "sll     zero,zero,$0000" */
  125.                 sprintf( buffer, "nop" );
  126.             }
  127.             else
  128.             {
  129.                 sprintf( buffer, "sll     %s,%s,$%02x", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], INS_SHAMT( op ) );
  130.             }
  131.             break;
  132.         case FUNCT_SRL:
  133.             sprintf( buffer, "srl     %s,%s,$%02x", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], INS_SHAMT( op ) );
  134.             break;
  135.         case FUNCT_SRA:
  136.             sprintf( buffer, "sra     %s,%s,$%02x", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], INS_SHAMT( op ) );
  137.             break;
  138.         case FUNCT_SLLV:
  139.             sprintf( buffer, "sllv    %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ] );
  140.             break;
  141.         case FUNCT_SRLV:
  142.             sprintf( buffer, "srlv    %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ] );
  143.             break;
  144.         case FUNCT_SRAV:
  145.             sprintf( buffer, "srav    %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ] );
  146.             break;
  147.         case FUNCT_JR:
  148.             sprintf( buffer, "jr      %s", s_cpugenreg[ INS_RS( op ) ] );
  149.             break;
  150.         case FUNCT_JALR:
  151.             sprintf( buffer, "jalr    %s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ] );
  152.             break;
  153.         case FUNCT_SYSCALL:
  154.             sprintf( buffer, "syscall $%05x", INS_CODE( op ) );
  155.             break;
  156.         case FUNCT_BREAK:
  157.             sprintf( buffer, "break   $%05x", INS_CODE( op ) );
  158.             break;
  159.         case FUNCT_MFHI:
  160.             sprintf( buffer, "mfhi    %s", s_cpugenreg[ INS_RD( op ) ] );
  161.             break;
  162.         case FUNCT_MTHI:
  163.             sprintf( buffer, "mthi    %s", s_cpugenreg[ INS_RS( op ) ] );
  164.             break;
  165.         case FUNCT_MFLO:
  166.             sprintf( buffer, "mflo    %s", s_cpugenreg[ INS_RD( op ) ] );
  167.             break;
  168.         case FUNCT_MTLO:
  169.             sprintf( buffer, "mtlo    %s", s_cpugenreg[ INS_RS( op ) ] );
  170.             break;
  171.         case FUNCT_MULT:
  172.             switch( INS_RD( op ) )
  173.             {
  174.             case 0:
  175.                 sprintf( buffer, "mult    %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  176.                 break;
  177.             }
  178.             break;
  179.         case FUNCT_MULTU:
  180.             switch( INS_RD( op ) )
  181.             {
  182.             case 0:
  183.                 sprintf( buffer, "multu   %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  184.                 break;
  185.             }
  186.             break;
  187.         case FUNCT_DIV:
  188.             switch( INS_RD( op ) )
  189.             {
  190.             case 0:
  191.                 sprintf( buffer, "div     %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  192.                 break;
  193.             }
  194.             break;
  195.         case FUNCT_DIVU:
  196.             switch( INS_RD( op ) )
  197.             {
  198.             case 0:
  199.                 sprintf( buffer, "divu    %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  200.                 break;
  201.             }
  202.             break;
  203.         case FUNCT_ADD:
  204.             sprintf( buffer, "add     %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  205.             break;
  206.         case FUNCT_ADDU:
  207.             sprintf( buffer, "addu    %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  208.             break;
  209.         case FUNCT_SUB:
  210.             sprintf( buffer, "sub     %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  211.             break;
  212.         case FUNCT_SUBU:
  213.             sprintf( buffer, "subu    %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  214.             break;
  215.         case FUNCT_AND:
  216.             sprintf( buffer, "and     %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  217.             break;
  218.         case FUNCT_OR:
  219.             sprintf( buffer, "or      %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  220.             break;
  221.         case FUNCT_XOR:
  222.             sprintf( buffer, "xor     %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  223.             break;
  224.         case FUNCT_NOR:
  225.             sprintf( buffer, "nor     %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  226.             break;
  227.         case FUNCT_SLT:
  228.             sprintf( buffer, "slt     %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  229.             break;
  230.         case FUNCT_SLTU:
  231.             sprintf( buffer, "sltu    %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
  232.             break;
  233.         }
  234.         break;
  235.     case OP_REGIMM:
  236.         switch( INS_RT( op ) )
  237.         {
  238.         case RT_BLTZ:
  239.             sprintf( buffer, "bltz    %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  240.             break;
  241.         case RT_BGEZ:
  242.             sprintf( buffer, "bgez    %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  243.             break;
  244.         case RT_BLTZAL:
  245.             sprintf( buffer, "bltzal  %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  246.             break;
  247.         case RT_BGEZAL:
  248.             sprintf( buffer, "bgezal  %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  249.             break;
  250.         }
  251.         break;
  252.     case OP_J:
  253.         sprintf( buffer, "j       $%08x", ( pc & 0xF0000000 ) + ( INS_TARGET( op ) << 2 ) );
  254.         break;
  255.     case OP_JAL:
  256.         sprintf( buffer, "jal     $%08x", ( pc & 0xF0000000 ) + ( INS_TARGET( op ) << 2 ) );
  257.         break;
  258.     case OP_BEQ:
  259.         sprintf( buffer, "beq     %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  260.         break;
  261.     case OP_BNE:
  262.         sprintf( buffer, "bne     %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  263.         break;
  264.     case OP_BLEZ:
  265.         switch( INS_RT( op ) )
  266.         {
  267.         case OP_BLEZ:
  268.             sprintf( buffer, "blez    %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  269.             break;
  270.         }
  271.         break;
  272.     case OP_BGTZ:
  273.         switch( INS_RT( op ) )
  274.         {
  275.         case OP_BGTZ:
  276.             sprintf( buffer, "bgtz    %s,$%08x", s_cpugenreg[ INS_RS( op ) ], pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  277.             break;
  278.         }
  279.         break;
  280.     case OP_ADDI:
  281.         sprintf( buffer, "addi    %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
  282.         break;
  283.     case OP_ADDIU:
  284.         sprintf( buffer, "addiu   %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
  285.         break;
  286.     case OP_SLTI:
  287.         sprintf( buffer, "slti    %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
  288.         break;
  289.     case OP_SLTIU:
  290.         sprintf( buffer, "sltiu   %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
  291.         break;
  292.     case OP_ANDI:
  293.         sprintf( buffer, "andi    %s,%s,$%04x", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], INS_IMMEDIATE( op ) );
  294.         break;
  295.     case OP_ORI:
  296.         sprintf( buffer, "ori     %s,%s,$%04x", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], INS_IMMEDIATE( op ) );
  297.         break;
  298.     case OP_XORI:
  299.         sprintf( buffer, "xori    %s,%s,$%04x", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], INS_IMMEDIATE( op ) );
  300.         break;
  301.     case OP_LUI:
  302.         sprintf( buffer, "lui     %s,$%04x", s_cpugenreg[ INS_RT( op ) ], INS_IMMEDIATE( op ) );
  303.         break;
  304.     case OP_COP0:
  305.         switch( INS_RS( op ) )
  306.         {
  307.         case RS_MFC:
  308.             sprintf( buffer, "mfc0    %s,%s",  s_cpugenreg[ INS_RT( op ) ], s_cp0genreg[ INS_RD( op ) ] );
  309.             break;
  310.         case RS_MTC:
  311.             sprintf( buffer, "mtc0    %s,%s",  s_cpugenreg[ INS_RT( op ) ], s_cp0genreg[ INS_RD( op ) ] );
  312.             break;
  313.         case RS_BC:
  314.             switch( INS_RT( op ) )
  315.             {
  316.             case RT_BCF:
  317.                 sprintf( buffer, "bc0f    $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  318.                 break;
  319.             case RT_BCT:
  320.                 sprintf( buffer, "bc0t    $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  321.                 break;
  322.             }
  323.             break;
  324.         default:
  325.             switch( INS_CO( op ) )
  326.             {
  327.             case 1:
  328.                 sprintf( buffer, "cop0    $%07x", INS_COFUN( op ) );
  329.  
  330.                 switch( INS_CF( op ) )
  331.                 {
  332.                 case 1:
  333.                     sprintf( buffer, "tlbr" );
  334.                     break;
  335.                 case 4:
  336.                     sprintf( buffer, "tlbwi" );
  337.                     break;
  338.                 case 6:
  339.                     sprintf( buffer, "tlbwr" );
  340.                     break;
  341.                 case 8:
  342.                     sprintf( buffer, "tlbp" );
  343.                     break;
  344.                 case 16:
  345.                     sprintf( buffer, "rfe" );
  346.                     break;
  347.                 }
  348.                 break;
  349.             }
  350.             break;
  351.         }
  352.         break;
  353.     case OP_COP1:
  354.         switch( INS_RS( op ) )
  355.         {
  356.         case RS_MFC:
  357.             sprintf( buffer, "mfc1    %s,%s",  s_cpugenreg[ INS_RT( op ) ], s_cp1genreg[ INS_RD( op ) ] );
  358.             break;
  359.         case RS_CFC:
  360.             sprintf( buffer, "cfc1    %s,%s",  s_cpugenreg[ INS_RT( op ) ], s_cp1ctlreg[ INS_RD( op ) ] );
  361.             break;
  362.         case RS_MTC:
  363.             sprintf( buffer, "mtc1    %s,%s",  s_cpugenreg[ INS_RT( op ) ], s_cp1genreg[ INS_RD( op ) ] );
  364.             break;
  365.         case RS_CTC:
  366.             sprintf( buffer, "ctc1    %s,%s",  s_cpugenreg[ INS_RT( op ) ], s_cp1ctlreg[ INS_RD( op ) ] );
  367.             break;
  368.         case RS_BC:
  369.             switch( INS_RT( op ) )
  370.             {
  371.             case RT_BCF:
  372.                 sprintf( buffer, "bc1f    $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  373.                 break;
  374.             case RT_BCT:
  375.                 sprintf( buffer, "bc1t    $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  376.                 break;
  377.             }
  378.             break;
  379.         default:
  380.             switch( INS_CO( op ) )
  381.             {
  382.             case 1:
  383.                 sprintf( buffer, "cop1    $%07x", INS_COFUN( op ) );
  384.                 break;
  385.             }
  386.             break;
  387.         }
  388.         break;
  389.     case OP_COP2:
  390.         switch( INS_RS( op ) )
  391.         {
  392.         case RS_MFC:
  393.             sprintf( buffer, "mfc2    %s,%s",  s_cpugenreg[ INS_RT( op ) ], s_cp2genreg[ INS_RD( op ) ] );
  394.             break;
  395.         case RS_CFC:
  396.             sprintf( buffer, "cfc2    %s,%s",  s_cpugenreg[ INS_RT( op ) ], s_cp2ctlreg[ INS_RD( op ) ] );
  397.             break;
  398.         case RS_MTC:
  399.             sprintf( buffer, "mtc2    %s,%s",  s_cpugenreg[ INS_RT( op ) ], s_cp2genreg[ INS_RD( op ) ] );
  400.             break;
  401.         case RS_CTC:
  402.             sprintf( buffer, "ctc2    %s,%s",  s_cpugenreg[ INS_RT( op ) ], s_cp2ctlreg[ INS_RD( op ) ] );
  403.             break;
  404.         case RS_BC:
  405.             switch( INS_RT( op ) )
  406.             {
  407.             case RT_BCF:
  408.                 sprintf( buffer, "bc2f    $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  409.                 break;
  410.             case RT_BCT:
  411.                 sprintf( buffer, "bc2t    $%08x", pc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 ) );
  412.                 break;
  413.             }
  414.             break;
  415.         default:
  416.             switch( INS_CO( op ) )
  417.             {
  418.             case 1:
  419.                 sprintf( buffer, "cop2    $%07x", INS_COFUN( op ) );
  420.  
  421.                 switch( GTE_OP( op ) )
  422.                 {
  423.                 case 0x0100001:
  424.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  425.                     {
  426.                         sprintf( buffer, "rtps" );
  427.                     }
  428.                     break;
  429.                 case 0x0200030:
  430.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  431.                     {
  432.                         sprintf( buffer, "rtpt" );
  433.                     }
  434.                     break;
  435.                 case 0x0400012:
  436.                     sprintf( buffer, "mvmva%s %s,%s,%s,%s", s_gtesf[ GTE_SF( op ) ], s_gtev[ GTE_V( op ) ], s_gtemx[ GTE_MX( op ) ], s_gtecv[ GTE_CV( op ) ], s_gtelm[ GTE_LM( op ) ] );
  437.                     break;
  438.                 case 0x0600029:
  439.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  440.                     {
  441.                         sprintf( buffer, "dcpl" );
  442.                     }
  443.                     break;
  444.                 case 0x0700010:
  445.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  446.                     {
  447.                         sprintf( buffer, "dpcs" );
  448.                     }
  449.                     break;
  450.                 case 0x0900011:
  451.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  452.                     {
  453.                         sprintf( buffer, "intpl" );
  454.                     }
  455.                     break;
  456.                 case 0x0a00028:
  457.                     if( GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 1 )
  458.                     {
  459.                         sprintf( buffer, "sqr%s", s_gtesf[ GTE_SF( op ) ] );
  460.                     }
  461.                     break;
  462.                 case 0x0c0001e:
  463.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 1 )
  464.                     {
  465.                         sprintf( buffer, "ncs" );
  466.                     }
  467.                     break;
  468.                 case 0x0d00020:
  469.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 1 )
  470.                     {
  471.                         sprintf( buffer, "nct" );
  472.                     }
  473.                 break;
  474.                 case 0x0e00013:
  475.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 1 )
  476.                     {
  477.                         sprintf( buffer, "ncds" );
  478.                     }
  479.                     break;
  480.                 case 0x0f00016:
  481.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 1 )
  482.                     {
  483.                         sprintf( buffer, "ncdt" );
  484.                     }
  485.                     break;
  486.                 case 0x0f0002a:
  487.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  488.                     {
  489.                         sprintf( buffer, "dpct" );
  490.                     }
  491.                     break;
  492.                 case 0x100001b:
  493.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 1 )
  494.                     {
  495.                         sprintf( buffer, "nccs" );
  496.                     }
  497.                     break;
  498.                 case 0x110003f:
  499.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 1 )
  500.                     {
  501.                         sprintf( buffer, "ncct" );
  502.                     }
  503.                     break;
  504.                 case 0x1200014:
  505.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 1 )
  506.                     {
  507.                         sprintf( buffer, "cdp" );
  508.                     }
  509.                     break;
  510.                 case 0x130001c:
  511.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 1 )
  512.                     {
  513.                         sprintf( buffer, "cc" );
  514.                     }
  515.                     break;
  516.                 case 0x1400006:
  517.                     if( GTE_SF( op ) == 0 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  518.                     {
  519.                         sprintf( buffer, "nclip" );
  520.                     }
  521.                     break;
  522.                 case 0x150002d:
  523.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  524.                     {
  525.                         sprintf( buffer, "avsz3" );
  526.                     }
  527.                     break;
  528.                 case 0x160002e:
  529.                     if( GTE_SF( op ) == 1 && GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  530.                     {
  531.                         sprintf( buffer, "avsz4" );
  532.                     }
  533.                     break;
  534.                 case 0x170000c:
  535.                     if( GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  536.                     {
  537.                         sprintf( buffer, "op%s", s_gtesf[ GTE_SF( op ) ] );
  538.                     }
  539.                     break;
  540.                 case 0x190003d:
  541.                     if( GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  542.                     {
  543.                         sprintf( buffer, "gpf%s", s_gtesf[ GTE_SF( op ) ] );
  544.                     }
  545.                     break;
  546.                 case 0x1a0003e:
  547.                     if( GTE_MX( op ) == 0 && GTE_V( op ) == 0 && GTE_CV( op ) == 0 && GTE_LM( op ) == 0 )
  548.                     {
  549.                         sprintf( buffer, "gpl%s", s_gtesf[ GTE_SF( op ) ] );
  550.                     }
  551.                     break;
  552.                 }
  553.             }
  554.             break;
  555.         }
  556.         break;
  557.     case OP_LB:
  558.         sprintf( buffer, "lb      %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  559.         break;
  560.     case OP_LH:
  561.         sprintf( buffer, "lh      %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  562.         break;
  563.     case OP_LWL:
  564.         sprintf( buffer, "lwl     %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  565.         break;
  566.     case OP_LW:
  567.         sprintf( buffer, "lw      %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  568.         break;
  569.     case OP_LBU:
  570.         sprintf( buffer, "lbu     %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  571.         break;
  572.     case OP_LHU:
  573.         sprintf( buffer, "lhu     %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  574.         break;
  575.     case OP_LWR:
  576.         sprintf( buffer, "lwr     %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  577.         break;
  578.     case OP_SB:
  579.         sprintf( buffer, "sb      %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  580.         break;
  581.     case OP_SH:
  582.         sprintf( buffer, "sh      %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  583.         break;
  584.     case OP_SWL:
  585.         sprintf( buffer, "swl     %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  586.         break;
  587.     case OP_SW:
  588.         sprintf( buffer, "sw      %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  589.         break;
  590.     case OP_SWR:
  591.         sprintf( buffer, "swr     %s,%s(%s)", s_cpugenreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  592.         break;
  593.     case OP_LWC1:
  594.         sprintf( buffer, "lwc1    %s,%s(%s)", s_cp1genreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  595.         break;
  596.     case OP_LWC2:
  597.         sprintf( buffer, "lwc2    %s,%s(%s)", s_cp2genreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  598.         break;
  599.     case OP_SWC1:
  600.         sprintf( buffer, "swc1    %s,%s(%s)", s_cp1genreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  601.         break;
  602.     case OP_SWC2:
  603.         sprintf( buffer, "swc2    %s,%s(%s)", s_cp2genreg[ INS_RT( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
  604.         break;
  605.     }
  606.     return pc - oldpc;
  607. }
  608.